1. Field of the Invention
The present invention relates to a semiconductor nonvolatile memory device. More particularly, the present invention is related to a memory device in the form of a nonvolatile RAM (NVRAM), in which a volatile memory, for example, a static random access memory (SRAM) or dynamic random access memory (DRAM) and an electrically erasable and programmable read only memory (EEPROM or E.sup.2 PROM) are combined on a one to one basis.
2. Description of the Related Art
In general, a memory cell array of an NVRAM is composed of a number of memory cell units in which an SRAM cell and an EEPROM cell are combined, and before the power source is turned OFF, the content of the SRAM cell is transferred to the EEPROM cell, thus rendering the device nonvolatile.
That is, when the power source is ON, the SRAM carries out a read/write operation as a conventional SRAM, and before the power source is turned OFF, the data in the SRAM is written into the EEPROM, and utilizing the nonvolatile characteristic, data is held therein while the power source is OFF. When the power source is again switched ON, the data in the EEPROM is recalled to the SRAM and a conventional read/write operation carried out.
To control such a currently used NVRAM, the following method is utilized.
For example, when two sorts of signals, i.e., a store signal ST (inverted ST) and a recall signal RC (inverted RC), are used, and a store signal ST falls to a LOW level, the content of the SRAM is transferred to the EEPROM. Conversely, when a recall signal RC falls to a LOW level, the content of the EEPROM is transferred to the SRAM.
A nonvolatile enable signal NE (inverted NE) is combined with a respective signal between a write enable signal WE (inverted WE), a chip enable signal CE (inverted CE) and an output enable signal OE(inverted OE), to realize either the above-noted store signal mode or recall mode and therefore, a control pin must be utilized for this procedure.